1. Field of the Invention
The present invention concerns a method of forming trench isolation having a polishing step and a method of manufacturing a semiconductor device having a polishing step. The present invention can be applied to the formation of trench isolation (trench type inter-device separation) in various kinds of electronic materials, a method of manufacturing various kinds of semiconductor devices braving trench isolation, as well as a method of manufacturing various kinds of semiconductor devices having a recess burying step and a subsequent flattening and polishing step. Further, it can be utilized as a method of manufacturing a semiconductor device having a polishing step including a step of burying recesses defined with a plurality of protrusion patterns (that is, defined between each of protrusion patterns) by a burying material and a step of flattening the burying material formed on the protrusion patterns.
2. Description of the Prior Art
Polishing techniques have a wide application of use and it can be utilized, for example, for flattening unevenness resulting in a substrate such as a semiconductor substrate during manufacturing a semiconductor device (refer, for example, to Japanese Patent Laid Open sho 63-39835).
On the other hand, capacitances of devices have been increased in the field of semiconductor devices and various kinds of techniques have been developed in order to increase the capacitance while minimizing chip area to as small as possible and, for example, a multi-layered wiring technique is indispensable therefor. In the multi-layered wiring technique, it is extremely important to flatten the underlying substrate in order to prevent disconnection of the multi-layered wiring. This is because unevenness on the underlying substrate, if any, will lead to occurrence of wire disconnection at a step caused by the unevenness (so-called step disconnection). In order to flatten the underlying substrate satisfactorily, flattening at the initial stage is important.
For attaining the above-mentioned object, there has been considered, for example, a flat trench isolation. Trench isolation is a technique for inter-device isolation by burying an insulator in trenches formed on a semiconductor substrate and it is advantageous for higher degree integration since fine trenches can be formed. However, after burying, i.e. filling, the trenches, it is necessary to remove protrusions of the burying material deposited at the portions other than in the trenches for attaining a flattened surface. The trench can be formed as a recess between two protrusion patterns but, when a burying material is buried, i.e. filled, in the recess (trench), since the burying material is also deposited on the protrusion patterns other than the trench to form a protruding portion, it has to be flattened. A method as shown in FIGS. 11a-11c is known as a method of forming a flat trench isolation.
In this method, as shown in FIG. 11(a), a thin silicon oxide film 2 and a thin silicone nitride film 3 are formed on a semiconductor substrate 1, then trenches 41, 42 and 43 are formed by etching using a photolithographic step and, subsequently, an inner wall oxide film, that is, the silicon oxide layer 2 is formed by oxidation to provide a semiconductor substrate.
Then, as shown in FIG. 11(b), a burying material 5 is deposited in the trenches 41-43 by a deposition means, for example, CVD to obtain a structure as shown in the figure. In this case, the burying material 5 is deposited to a large thickness also on the portions other than in the trenches 42-43 to result in protrusions 51.
Accordingly, as shown in FIG. 11(c), the protrusions 51 are removed by polishing to flatten the surface by polishing. In a case where silicone oxide is used as the burying material 5, a silicon nitride film 3 having a polishing rate lower than that of silicon dioxide may be used for instance as a stopper layer for polishing.
Such a method is applied, in addition to the trench isolation process, also to other processes for forming flat interlayer insulation films such as formation of a trench capacitor accompanying trench burying, formation of trench contact (trench plug) or formation of a layer by a blanket W-CVD process.
However, in a case where a wide recessed region (1) and a narrow protruding region (2) are formed as shown in FIG. 12(a). When polishing is applied directly after burying the trenches 41-43, the burying material 52 (SiO2 or the like) that is not removed completely remains in the central portion of the burying material 5 on the wide protruding region (1), and SiO2 or the like which is the burying material 52 is raised to result in occurrence of particles when the stopper layer 2 (for example) Si3N4 is removed by hot phosphoric acid in the succeeding step.
As a countermeasure for overcoming the problem, for instance, IBM has presented the following technique in IEDM in 1989 (IEDM 89, pp 61-64). That is, as shown in FIG. 13(a), a block resist 31 is formed in the recess of CVD-SiO2 as the burying material 5, on which a resist coating film 3 is formed which is then etched back. Thus, a structure as shown in FIG. 13(b) is obtained. Then, it is flattened by polishing to obtain a flattened structure as shown in FIG. 13(c). However, in this method, if a patterning for the block resist is displaced to form a resist out of the recess as shown by reference numeral 31xe2x80x2 in FIG. 13(d), no sufficient flatness can be obtained even if a resist coating film 3xe2x80x2 is formed, so that the burying material 5 does not become flat as shown in FIG. 13(e) and, as a result, it is difficult to flatten by means of polishing.
In addition, there is also the following problem. That is, the flattening technique by polishing involves a problem that the extent of polishing depends on the underlying pattern and sometimes it results in unevenness. Description will now be made to the problem with reference to FIG. 14.
In FIG. 14, trenches 41-43 are formed as recesses between each of protrusion patterns 61-64. The protrusion patterns 61-64 function as a stopper during polishing. As shown in FIG. 14, the density of the protrusion pattern 61 is small or sparse in the portion A of the figure in which the protrusion pattern 61 is present. In the portion B shown in the figure in which the protrusion patterns 62-64 are present, a ratio of the protrusion patterns per unit area (the area ratio of the protrusion patterns) is great and, accordingly, the density of the protrusion pattern is large or dense. In the illustrated embodiment, since silicon nitride or the like is used as a polishing stopper layer and is formed on the protrusion patterns 61-64, the area of the stopper layer 3 per unit area is small and, accordingly, the density thereof is sparse in the illustrated portion A. On the other hand, since the area of the stopper layer 3 per unit area is large, the density of the polishing stopper 3 is dense in the illustrated portion B shown in the figure. If there is unevenness of the ratio of the polishing stopper layer 3 (which exists for each of the protrusion patterns 61-64), polishing tends to become uneven.
For instance, in a peripheral circuit, if the area ratio per unit area of a protrusion pattern present at the periphery that functions as a polishing stopper layer is low (for example, in a case of the region A in FIG. 14), since polishing pressure is concentrated during polishing on the protrusion pattern (stopper layer), the polishing rate is increased, so that mere selection of the ratio of the protrusion pattern (stopper layer) is unsufficient and the isolation pattern 61 is worn off as shown in FIG. 14(b) so that it no longer has its intended effect as the stopper layer. As a result, the region A is concaved and a uniform and satisfactory flattening can not be attained as shown in FIG. 14(b).
Accordingly, there is a demand for a technique capable of attaining satisfactory flattening by polishing also in a case where the distribution of the polishing stopper layer shows unevenness (for instance, in a case where there is an unevenness for the density of protrusion patterns and, accordingly, there is an unevenness in the ratio of the polishing stopper layer) and also for a portion in which the area ratio is low, that is, a portion of a circuit pattern in which the portion that functions as the polishing stopper is sparse.
It is an object of the present invention to overcome the foregoing problems in the prior art and provide a means capable of flattening without leaving burying material on a wide (long) protrusion region which is thereby capable of forming trench isolation of a satisfactory flatness, as well as a method of manufacturing a semiconductor device formed with such trench isolation.
Another object of the present invention is to provide a method of manufacturing a semiconductor device having a polishing step of performing flattening after a burying step, wherein a satisfactory flattened shape can be formed even in a case where a distribution of a portion which is to serve as a polishing stopper on a portion to be polished has unevenness, also in a portion in which an area ratio of the stopper layer per unit area is low.
The foregoing objects are attained by the present invention, concerning a method of forming trench isolation including a burying step of burying trenches by a deposition means for conducting etching and deposition simultaneously and a polishing step of flattening a burying material by polishing, wherein the method comprises at least an isotropic etching step for isotropically etching the burying material before the polishing step.
The foregoing objects are attained by the present invention, concerning a method of forming trench isolation, wherein trenches are formed in a structure which has an etching stopper layer comprising a three-layered structure, and in which the upper layer of the etching stopper layer comprises a film having a polishing rate slower than that of the burying material and an etching rate also slower than that of the burying material, an intermediate layer of the etching stopper layer comprises a film having an etching rate slower than that of the upper layer, and a lower layer of the etching stopper layer comprises a film having an etching rate slower than that of the intermediate layer and faster than that of the substrate.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device of forming trench isolation by using the method of forming trench isolation.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device for forming trench isolation, which comprises a burying step of burying trenches by a bias ECR-CVD process, an isotropic etching step of isotropically etching a burying material thereby etching the burying material on a wide protrusion region and a polishing step of flattening the burying material by polishing.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device for forming trench isolation by forming trenches in a structure, in which a substrate to form trench isolation has an etching stopper layer comprising a three-layered structure, in which the upper layer of the etching stopper layer comprises a silicon nitride, an intermediate layer of the etching stopper layer comprises polysilicon and a lower layer of the etching stopper layer comprises a silicon dioxide film.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device having a polishing step including a step of burying recesses defined with a plurality of protrusion patterns by a burying material and a polishing step of flattening the burying material formed on the protrusion patterns by polishing, which comprises previously forming a pattern that constitutes a stopper layer for polishing and that is not intended to directly function as a wiring or insulation portion, to a portion in which the density of the stopper layer for polishing is sparse.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device having a polishing step, wherein the pattern, which comprises a previously formed a pattern that constitutes a stopper layer for polishing and that is not intended to directly function as a wiring or insulation portion is finally removed by polishing. The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device having a polishing step including a step of burying recesses defined with a plurality of protrusion patterns with a burying material on a semiconductor substrate having the plurality of protrusion patterns comprising a wide protrusion region and narrow protrusion region, and a step of flattening the burying material formed on the protrusion patterns by polishing, wherein the method comprises a step of previously forming a pattern that constitutes a stopper layer for polishing and that is finally removed on a portion in which the density of the stopper layer for polishing is sparse, and a step of at least partially etching the burying material on the wide protrusion region prior to the flattening step by polishing.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device in which a plurality of protrusion patterns are formed on a substrate and trenches comprising recesses defined therebetween are buried, wherein a pattern as a stopper layer for polishing is previously formed on a portion in which the density of the protrusion patterns formed with the stopper layer for polishing is sparse to obtain a structure having the protrusions being uniformly distributed, thereby making the area ratio of the stopper layer uniform, subsequently, burying material is deposited and then the burying material on the protrusion patterns and the previously formed patterns are removed by polishing to obtain a flattened structure.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device, wherein the burying material Is silicon dioxide and the layer which serves as the polishing stopper comprises silicon nitride.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device, wherein the burying material is silicon dioxide and a bias ECR-CVD process is used for the formation of the burying material.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device, wherein the burying material is silicon dioxide and an atmosphere pressure CVD process is used for the formation of the burying material.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device, wherein CVD silicon dioxide is formed by using an organic silicon gas. The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device, wherein the layer constituting the polishing stopper comprises silicon nitride and a step of at least partially removing the burying material on the wide protrusion region prior to the flattening step by polishing utilizes a means of applying isotropic etching while masking other positions than the etched portion with a resist.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device including a burying step in which a recess burying material is deposited by a deposition means on a substrate formed with a plurality of recesses and a polishing step in which the burying material is flattened by polishing, wherein the method comprises a resist depositing step of depositing a resist on the substrate after the polishing step, a resist pattern forming step of forming a resist pattern while exposing the burying material remaining in the portions other than the recesses to be buried, and a removing step of removing the burying material remaining on the portions other than in the recesses to be buried by using the resist pattern as a mask.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device including a burying step for depositing a recess burying material by a deposition means on a substrate formed with a plurality of recesses and a polishing step of flattening the burying material by polishing, wherein the method comprises a flattened layer forming step of forming a flattened layer on the substrate, and an etching back step for etching back given that the etching rate is equal between the flattened layer and the burying material.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device which comprises burying silicon dioxide as the burying material into a plurality of recesses on a substrate having a silicon nitride film to serve as a stopper layer during polishing by a base CR-CVD process and then conducting a polishing step for flattening the burying material by polishing, conducting a resist forming step of forming a resist on a substrate after the polishing step and a resist pattern forming step of forming a resist pattern while exposing the burying material remaining on the portions other than in the recesses to be buried as the burying material not removed completely and, subsequently, conducting a removing step of removing the burying material remaining on the portion other than in the recesses to be buried by using the resist pattern as a mask, thereby conducting burying and flattening with the residue of the burying material removed completely.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device which comprises a burying step of forming a recess burying material by depositing silicon dioxide by a bias ECR-CVD process on a substrate in which a plurality of recesses are formed and on which a silicon nitride film is formed as a stopper layer during polishing, a polishing step of flattening the burying material by polishing, a flattened layer forming step of forming a flattened layer on a substrate by a resist or SOG and an etching back step of etching back given that the etching rates are equal between the flattened layer and the burying material.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device having a polishing step including a step of forming a plurality of protrusion patterns each having a stopper layer for polishing in the upper portion, a step of burying recesses defined with a plurality of protrusion patterns by a burying material and a step of flattening the burying material formed on the protrusion patterns by polishing, wherein the method comprises forming a second polishing stopper layer at least on the recess burying material after burying the recesses.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device including a step of forming a plurality of protrusion patterns each having a stopper layer for polishing in the upper portion, a step of burying a plurality of recesses comprising wide recesses and narrow recesses defined with a plurality of protrusion patterns by a burying material and a step of flattening the burying material formed on the protrusion patterns by polishing, wherein the method comprises forming a second stopper layer for polishing at least on the entire surface of the recess burying material after burying the recesses.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device which comprises forming a plurality of protrusion patterns on a substrate having a silicon nitride layer as a stopper layer for polishing and a poly-Si layer as an etching stopper layer of the silicon nitride layer in the upper portion, forming silicon dioxide as a burying material in recesses defined with a plurality of protrusion patterns by a CVD process, burying the recesses, subsequently, forming a second stopper layer for polishing over the entire surface, leaving a second stopper layer for polishing only on the burying material in a wide recess in a portion in which the density of the stopper layer for polishing is sparse by an etching step using a resist, and, thereafter, flattening the burying material formed on the recesses by polishing.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device, where silicon dioxide as the burying material is formed by a O3-TEOS CVD process.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device, wherein the burying material and the stopper layer for polishing are formed by a CVD process.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device, wherein the burying material and the stopper layer for polishing are formed by a deposition means for applying etching and deposition simultaneously.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device, wherein the deposition means for applying etching and deposition simultaneously is a bias ECR-CVD process.
The foregoing objects are attained by the present invention, concerning a method of manufacturing a semiconductor device, wherein the second stopper layer for polishing is formed over the entire surface of the recesses that constitute trenches.
According to the present invention, most of the material to be polished on the wide (long) protrusion region is removed in the etching step prior to the polishing step and, since all of the remaining portions to be polished are in a protruding shape, the polishing rate therefor is faster than that for the flattened surface to facilitate flattening. This enables flattening of formations that provide isolation.
For instance, the upper layer of the etching stopper layer functions as an etching stopper during etching of the burying material and, further, the intermediate layer 22 functions as a stopper for the upper layer 23 (refer to FIG. 2) and the lower layer functions as an etching stopper to the intermediate layer 22 and, accordingly, etching of the burying material can be performed till the surface of the stopper layer is exposed and, further, the burying material remaining on the protrusion region can be removed completely without requiring an etching back step.
Further, according to the present invention, a semiconductor device having satisfactorily flattened trench isolation can be obtained. Further, according to the present invention, a pattern that functions as a stopper layer for polishing and that is not intended directly to function as a wiring or insulation portion (which hereinafter is sometimes referred to as a dummy pattern)is formed, for example, on a portion in which the density of the protrusion pattern that serves as a polishing stopper is sparse, previously before polishing, for example, before deposition of the burying material by CVD or the like, so that the effect of the stopper layer can be made nearly uniform over the entire surface of the portion to be polished, the dummy pattern is preferably formed such that the area ratio of the stopper layer is greater than a predetermined ratio and then the polishing step is performed. Accordingly, a satisfactorily flattened shape can be formed.
Therefore, according to the present invention, it is possible to form a satisfactory flattened shape even in a case where the area ratio of the polishing stopper layer per unit area in the portion to be polished is low.
Further, according to the present invention, the material to be polished on the wide (long) protrusion region, if it remains after polishing, can easily be removed by a removed step using a resist pattern as a mask to conduct flattening, by which It is possible to manufacture a semiconductor device in which flat burying is attained.
Further, according to the present invention, the material to be polished on the wide (long) protrusion region, if it remains after polishing, can be easily removed by the etching back step to achieve flattening. This enables the manufacture a semiconductor device having flat burying of trenches.
Further, according to the present invention, after burying the recesses and depositing the burying material, for example, by CVD, the second polishing stopper layer is formed at least on the recess burying material, for example, on the recess burying material in a portion where the density of the polishing stopper layer is sparse, by which the stopper function can be made nearly uniform over the entire surface of the portion to be polished, the area ratio of the stopper layer can be increased preferably to greater than a predetermined ratio and, thereafter, polishing is performed. Consequently, a uniform and satisfactorily flattened shape can be obtained.
Therefore, according to the present invention, it is possible to form a satisfactorily flattened shape even in a case where the area ratio of the polishing stopper layer per unit area of the polished portion is low. Further, according to the present invention, after burying the recesses, for example, after depositing the burying material by CVD or the like, a second polishing stopper layer is formed at least over the entire surface of the recess burying material, so that the stopper function can be made nearly uniform over the entire surface of the polished portion and the area ratio of the stopper can be increased, preferably, to greater than a predetermined ratio and, subsequently, polishing is performed. Accordingly, a uniform and satisfactorily flattened shape is obtained.
Therefore, according to the present invention, a satisfactorily flattened shape can be formed even in a case where the area ratio of the polishing stopper layer per unit area of the polished portion is low.